// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    : fp_and_sch_top.v
// Module name  : fp_and_sch_top
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/10/12
// Version      :  V 1.0 
// 
//Abstract      :  \u5305\u542b\u6d41\u5206\u7c7b\u3001\u5206\u7ec4\u5904\u7406\u3001\u8f6c\u53d1\u8868\u3001\u961f\u5217\u8c03\u5ea6
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 	v1.1 zhangjianyuan 4.19
//
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module fp_and_sch_top(
	//sysrem input/output
	input  wire 		clk  ,
	input  wire 		rst_n,
	output wire         fp_sch_init_done,
    input  wire [11:0]  ram_dp_cfg_register,
    input  wire [ 9:0]  ram_2p_cfg_register,
    input wire [6:0] rf_2p_cfg_register ,
    //ME1-ME6
    `ifndef NO_CPU_MODE 
    input  wire [31:0]                np_cpu_wr_data              ,
    input  wire [16:0]                np_cpu_addr                 ,
    input  wire [ 1:0]                np_cpu_ram_ctr              ,
    output wire [31:0]                np_cpu_rd_data              ,
	output reg fp_sch_rd_vld ,
	`else
    input  wire [31:0]                np_cpu_wr_data              ,
    input  wire [16:0]                np_cpu_addr                 ,
    input  wire [ 1:0]                np_cpu_ram_ctr              ,
    output wire [31:0]                np_cpu_rd_data              ,
	`endif
    //\u56db\u8868\u540c\u6b65
    output wire [9:0]   bus1_table_addr2            ,
    output wire [9:0]   bus1_table_ram_addr_convert ,
    output wire [71:0]  bus1_table_data2            ,
    output wire [71:0]  bus1_table_ram_data_convert ,
    output wire         bus1_table_wren2            ,
    output wire         bus1_table_ram_wr_en_convert,
    input  wire [9:0]   bus2_table_addr2            ,
    input  wire [9:0]   bus2_table_ram_addr_convert ,
    input  wire [71:0]  bus2_table_data2            ,
    input  wire [71:0]  bus2_table_ram_data_convert ,
    input  wire         bus2_table_wren2            ,
    input  wire         bus2_table_ram_wr_en_convert,
    input  wire [9:0]   bus3_table_addr2            ,
    input  wire [9:0]   bus3_table_ram_addr_convert ,
    input  wire [71:0]  bus3_table_data2            ,
    input  wire [71:0]  bus3_table_ram_data_convert ,
    input  wire         bus3_table_wren2            ,
    input  wire         bus3_table_ram_wr_en_convert,
    input  wire [9:0]   bus4_table_addr2            ,
    input  wire [9:0]   bus4_table_ram_addr_convert ,
    input  wire [71:0]  bus4_table_data2            ,
    input  wire [71:0]  bus4_table_ram_data_convert ,
    input  wire         bus4_table_wren2            ,
    input  wire         bus4_table_ram_wr_en_convert,

    `ifdef NO_CPU_MODE
    	//\u914d\u7f6e\u5355\u64ad\u8f6c\u53d1\u8868
    input  wire [ 11:0] CPU_unicam_addr,
    output wire [ 31:0] CPU_unicam_dout,
    input  wire         CPU_unicam_wren,
    input  wire [ 31:0] CPU_unicam_din ,
    input  wire         CPU_unicam_live_val,
    input  wire [ 31:0] CPU_unicam_live_time,
    	//\u914d\u7f6e\u7ec4\u64ad\u8f6c\u53d1\u8868
    input  wire         CPU_mulcam_wren,
    input  wire [ 31:0] CPU_mulcam_modify,
    input  wire [ 31:0] CPU_mulcam_group_mac,
    input  wire [ 31:0] CPU_mulcam_member,
    input  wire         CPU_mulcam_rden,
    input  wire [ 11:0] CPU_mulcam_addr,
    output wire [ 31:0] CPU_mulcam_dout,
    	//\u914d\u7f6eDWRR\u8c03\u5ea6\u4ee5\u53ca\u6743\u91cd
    input  wire         DWRR_en,
    input  wire [ 15:0] WEIGHT7,
    input  wire [ 15:0] WEIGHT6,
    input  wire [ 15:0] WEIGHT5,
    input  wire [ 15:0] WEIGHT4,
    input  wire [ 15:0] WEIGHT3,
    input  wire [ 15:0] WEIGHT2,
    input  wire [ 15:0] WEIGHT1,
    input  wire [ 15:0] WEIGHT0,
    //\u914d\u7f6e\u961f\u5217\u8c03\u5ea6\u95e8\u9650
    //	enqueue
    output wire [  2:0] query_CPU_node_minmax_threshold,  //\u8282\u70b9\u6700\u5c0f\u6700\u5927\u95e8\u9650
		input  wire [ 31:0] CPU_node_minmax_threshold_data ,
		output wire [  5:0] query_CPU_queue_max_threshold  ,  //\u961f\u5217\u6700\u5927\u95e8\u9650
		input  wire [ 31:0] CPU_queue_max_threshold_data   ,
		input  wire [ 31:0] CPU_BD_public_length           ,  //BD\u5171\u4eab\u533a\u5927\u5c0f
		//	dequeue
		output wire [  2:0] query_CPU_node_min_threshold,
		input  wire [ 31:0] CPU_node_min_threshold_data ,
		//cpu_register
		output wire [31:0]  ro_reg_np_freeblocknumber_register	,
		output wire [31:0]	ro_reg_np_mac_enqueue_cnt 			,	   
		output wire [31:0]	ro_reg_np_mac_enqueue_fail_cnt 		, 
		output wire [31:0]	ro_reg_np_enqueue_num 				,
		output wire [31:0]  ro_reg_np_dequeue_num 				,		
		output wire [31:0]  ro_reg_np_max_rx_length 			,
		output wire [31:0]  ro_reg_np_max_tx_length   			,
    output wire [31:0]  rx_frame_cnt_node_0                 ,
    output wire [31:0]  rx_frame_cnt_node_1                 ,
    output wire [31:0]  rx_frame_cnt_node_2                 ,
    output wire [31:0]  rx_frame_cnt_node_3                 ,
    output wire [31:0]  rx_frame_cnt_node_4                 ,
    output wire [31:0]  tx_frame_cnt_node_0                 ,
    output wire [31:0]  tx_frame_cnt_node_1                 ,
    output wire [31:0]  tx_frame_cnt_node_2                 ,
    output wire [31:0]  tx_frame_cnt_node_3                 ,
    output wire [31:0]  tx_frame_cnt_node_4                 , 
    `endif
		//\u6570\u636e\u5e27\u4fe1\u606f
		input  wire 		 		 pkt_sop 		,
		input  wire 		 		 pkt_eop 		,
		input  wire          pkt_dsav       ,
		input  wire [255:0]  pkt_data 		,
		input  wire 		 pkt_dval 		,
		input  wire [  4:0]  pkt_mod 		,
		input  wire [  7:0]  src_node_id 	,  //\u67e5\u627e\u66f4\u65b0\u7ec4\u64ad\u8868\u7528
		output wire 		 		 pkt_rdy 		,  //\u5206\u7ec4\u5904\u7406\u6a21\u5757\u63a5\u6536\u6570\u636e\u51c6\u5907\u597d
		//with insert
		output wire         rx_rdy_insert     ,
		input  wire         rx_ff_sop_insert  ,
		input  wire         rx_ff_eop_insert  ,
		input  wire         rx_ff_dval_insert ,
		input  wire         rx_ff_dsav_insert ,
		input  wire [255:0] rx_ff_data_insert ,
		input  wire [  4:0] rx_ff_mod_insert  ,
		input  wire         insert_empty      ,                       
		input  wire [  7:0] des_node_id_insert, //\u63d2\u5165\u5e27\u76ee\u7684\u8282\u70b9\u53f7
		input  wire [  2:0] pri_insert        ,
		//with capture
		input  wire [ 15:0] capture_eth_type,
		input  wire         capture_rdy     , //\u6355\u83b7\u6a21\u5757\u4e0d\u5fd9\u4fe1\u53f7
		output wire [262:0] capture_data_o  ,     
		output wire         capture_dval    , //\u6355\u83b7\u5199\u6570\u636e\u6709\u6548\u4fe1\u53f7
		output wire         capture_en      ,
		output wire [ 10:0] cpt_frame_len   ,
		//with crossbar_ctrl_top
		input  wire 		uni_tx_rdy0     ,
		input  wire 		uni_tx_rdy1     ,
		input  wire 		uni_tx_rdy2     ,
		input  wire 		uni_tx_rdy3     ,
		input  wire 		mul_tx_rdy0     ,
		input  wire 		mul_tx_rdy1     ,
		input  wire 		mul_tx_rdy2     ,
		input  wire 		mul_tx_rdy3     ,
		output wire [255:0] emac_data_in    ,
		output wire         emac_data_wren  ,
		output wire [  5:0] rx_address_dpram,
		output wire [  3:0] mac_dest_port_in,
		output wire         mul_indicate    
	);

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

//WIRES
//\u521d\u59cb\u5316\u5b8c\u6210
wire unicam_init_done;
wire multicam_init_done;
wire queuesch_init_done;
//\u6d41\u5206\u7c7b\u4e0e\u5206\u7ec4\u5904\u7406--\u63a5\u6536\u8c03\u5ea6
wire         in_buf_val;
wire         multicast;
wire         schedule_start;
wire         frame_info_fifo_empty;
wire         frame_info_fifo_rden;
wire [ 31:0] frame_info_fifo_o;
wire [ 47:0] mac_src_addr;
wire [ 47:0] mac_des_addr;
wire [  7:0] src_node_id_o;
wire [128:0] ip_src_addr;
wire [128:0] ip_des_addr;
//\u63a5\u6536\u8c03\u5ea6--\u5355\u64ad\u8f6c\u53d1\u8868
wire [ 47:0] mac_sour;
wire [  3:0] port_sour;
wire [ 47:0] mac_dest;
wire         uni_addr_en;
wire         uni_busy;
(*mark_debug = "true"*) wire [  3:0] uni_outport;
(*mark_debug = "true"*) wire         uni_outport_en;
(*mark_debug = "true"*) wire         uni_lookup_fail;
//\u63a5\u6536\u8c03\u5ea6--\u7ec4\u64ad\u8f6c\u53d1\u8868
wire         multi_busy;
wire         multi_addr_en;
wire [  7:0] multi_outport;
wire         multi_outport_en;
//\u63a5\u6536\u8c03\u5ea6--\u961f\u5217\u8c03\u5ea6
(*mark_debug = "true"*)wire [ 31:0] rx_fifo_wdata;
(*mark_debug = "true"*)wire         rx_fifo_wren;
(*mark_debug = "true"*)wire         rx_fifo_full;
//\u5206\u7ec4\u5904\u7406--\u961f\u5217\u8c03\u5ea6
(*mark_debug = "true"*)wire         trans_start;
wire 	discard_start;
(*mark_debug = "true"*)wire         trans_ready;
wire [262:0] bus_data;   //sop(1bit)+eop(1bit)+mod(5bit)+data(256bit)
wire         bus_data_val;
wire         bus_data_end;
wire [ 10:0] frame_len_bus;
//\u5355\u64ad\u8f6c\u53d1\u8868\u51b2\u7a81\u54cd\u5e94
wire         broadcast_pkt_ack;
wire         unknow_pkt_ack;
wire [ 31:0] collision_port_1;
wire [ 31:0] collision_port_2;
wire [ 31:0] collision_mac_addr_1;
wire [ 31:0] collision_mac_addr_2;
wire         collision_wren;
wire frame_rd_end;

`ifndef NO_CPU_MODE
reg [31:0] np_data_out;
wire [31:0]fp_class_data_out  ;
wire [31:0]fp_class_data_in   ;
wire [16:0]fp_class_addr_in   ;
wire [1:0]fp_class_addr_ctrl ;
wire fp_class_rd_vld	;
wire [31:0]sch_data_out   ;
wire [31:0]sch_data_in    ;
wire [16:0]sch_addr_in    ;
wire [ 1:0]sch_addr_ctrl  ;
wire sch_rd_vld	;
wire [31:0]flc_data_out  ;
wire [31:0]flc_data_in   ;
wire [16:0]flc_addr_in   ;
wire [ 1:0]flc_addr_ctrl ;
wire flc_rd_vld	;
assign flc_data_in = np_cpu_wr_data ;
assign flc_addr_in = np_cpu_addr ;
assign flc_addr_ctrl = np_cpu_ram_ctr;

assign fp_class_data_in   = np_cpu_wr_data ;
assign fp_class_addr_in   = np_cpu_addr ;
assign fp_class_addr_ctrl = np_cpu_ram_ctr;


assign sch_data_in   = np_cpu_wr_data ;
assign sch_addr_in   = np_cpu_addr ;
assign sch_addr_ctrl = np_cpu_ram_ctr;

assign np_cpu_rd_data = np_data_out;
`else 
`endif


//½ÓÊÕµ÷¶ÈºÍÁ÷¿ØÁ¬½Ó
wire        result				 ;
wire        result_en			 ;
wire [1:0]  out_port_num		 ;
wire        frame_length_en	 	 ;
wire [10:0] frame_length 		 ;
wire [7:0]  node_flow_num		 ;
wire        lookup_fail		 	 ;
wire        class_flow_ctrl_en	 ;
wire [6:0]  class_flow_ctrl_num  ;
wire 	    do_not_flow_ctrl	 ;
//*********************
//INSTANTCE MODULE
//*********************
	fp_class_top inst_fp_class_top (
			.clk                       (clk),
			.rst_n                     (rst_n),
            .ram_dp_cfg_register(ram_dp_cfg_register),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            .rf_2p_cfg_register (rf_2p_cfg_register) ,
			//locallink\u683c\u5f0f\u6570\u636e\u5e27
			.pkt_sop                   (pkt_sop),
			.pkt_eop                   (pkt_eop),
			.pkt_dsav                  (pkt_dsav),
			.pkt_data                  (pkt_data),
			.pkt_dval                  (pkt_dval),
			.pkt_mod                   (pkt_mod),
			.src_node_id               (src_node_id),
			.pkt_rdy                   (pkt_rdy),
			`ifndef NO_CPU_MODE
			//CPU\u914d\u7f6e\u6d41\u5206\u7c7b\u89c4\u5219\u8868
            .np_cpu_rd_data 	(fp_class_data_out  )   ,
    		.np_cpu_wr_data  	(fp_class_data_in   )   ,
    		.np_cpu_addr  	    (fp_class_addr_in   )   ,
    		.np_cpu_ram_ctr	    (fp_class_addr_ctrl )   ,
			.fp_class_rd_vld    (fp_class_rd_vld	)   ,
			`else
			//CPU\u914d\u7f6e\u6d41\u5206\u7c7b\u89c4\u5219\u8868
            .np_cpu_wr_data(np_cpu_wr_data),
            .np_cpu_addr   (np_cpu_addr   ),
            .np_cpu_ram_ctr(np_cpu_ram_ctr),
            .np_cpu_rd_data(np_cpu_rd_data),
			`endif
            //\u5355\u64ad\u8868\u540c\u6b65\u63a5\u53e3
            .bus1_table_addr2            (bus1_table_addr2            ),
            .bus1_table_ram_addr_convert (bus1_table_ram_addr_convert ),
            .bus1_table_data2            (bus1_table_data2            ),
            .bus1_table_ram_data_convert (bus1_table_ram_data_convert ),
            .bus1_table_wren2            (bus1_table_wren2            ),
            .bus1_table_ram_wr_en_convert(bus1_table_ram_wr_en_convert),
            .bus2_table_addr2            (bus2_table_addr2            ),
            .bus2_table_ram_addr_convert (bus2_table_ram_addr_convert ),
            .bus2_table_data2            (bus2_table_data2            ),
            .bus2_table_ram_data_convert (bus2_table_ram_data_convert ),
            .bus2_table_wren2            (bus2_table_wren2            ),
            .bus2_table_ram_wr_en_convert(bus2_table_ram_wr_en_convert),
            .bus3_table_addr2            (bus3_table_addr2            ),
            .bus3_table_ram_addr_convert (bus3_table_ram_addr_convert ),
            .bus3_table_data2            (bus3_table_data2            ),
            .bus3_table_ram_data_convert (bus3_table_ram_data_convert ),
            .bus3_table_wren2            (bus3_table_wren2            ),
            .bus3_table_ram_wr_en_convert(bus3_table_ram_wr_en_convert),
            .bus4_table_addr2            (bus4_table_addr2            ),
            .bus4_table_ram_addr_convert (bus4_table_ram_addr_convert ),
            .bus4_table_data2            (bus4_table_data2            ),
            .bus4_table_ram_data_convert (bus4_table_ram_data_convert ),
            .bus4_table_wren2            (bus4_table_wren2            ),
            .bus4_table_ram_wr_en_convert(bus4_table_ram_wr_en_convert),
			//\u5355\u64ad\u8f6c\u53d1\u8868\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
			.mac_sour                (mac_sour),
			.port_sour               (port_sour),
			.mac_dest                (mac_dest),
			.uni_addr_en             (uni_addr_en    ),
			.uni_lookup_fail         (uni_lookup_fail),
			.unicam_busy             (uni_busy       ),
			.uni_outport             (uni_outport    ),
			.uni_outport_en          (uni_outport_en ),
			`ifdef NO_CPU_MODE
			//\u4e0eCPU\u914d\u7f6e\u63a5\u53e3
			.CPU_unicam_addr         (CPU_unicam_addr     ),
			.CPU_unicam_dout         (CPU_unicam_dout     ),
			.CPU_unicam_wren         (CPU_unicam_wren     ),
			.CPU_unicam_din          (CPU_unicam_din      ),
			.CPU_unicam_live_val     (CPU_unicam_live_val ),
			.CPU_unicam_live_time    (CPU_unicam_live_time),

			.uni_loopback_on_off     (1'b0/*uni_loopback_on_off*/),  //\u56de\u73af\u4e0d\u5f00\u542f\uff0cMAC\u5730\u5740\u5b66\u4e60\u51b2\u7a81
			.broadcast_pkt_pass      (1'b1/*broadcast_pkt_pass*/),  //\u5e7f\u64ad\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
			.broadcast_pkt_ack       (broadcast_pkt_ack),
			.unknow_pkt_pass         (1'b1/*unknow_pkt_pass*/),  //\u672a\u77e5\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
			.unknow_pkt_ack          (unknow_pkt_ack),

			.collision_detect_on_off (1'b1/*collision_detect_on_off*/),  //\u51b2\u7a81\u68c0\u6d4b\u5f00\u542f
			.collision_port_1        (collision_port_1),
			.collision_port_2        (collision_port_2),
			.collision_mac_addr_1    (collision_mac_addr_1),
			.collision_mac_addr_2    (collision_mac_addr_2),
			.collision_wren          (collision_wren),
			`endif
			//\u521d\u59cb\u5316\u5b8c\u6210
			.unicam_init_done        (unicam_init_done),
			//\u7ec4\u64ad\u8f6c\u53d1\u8868
			`ifdef NO_CPU_MODE
			//\u4e0eCPU\u914d\u7f6e\u63a5\u53e3
			.CPU_mulcam_wren             (CPU_mulcam_wren     ),
			.CPU_mulcam_modify           (CPU_mulcam_modify   ),
			.CPU_mulcam_group_mac        (CPU_mulcam_group_mac),
			.CPU_mulcam_member           (CPU_mulcam_member   ),
			.CPU_mulcam_rden             (CPU_mulcam_rden     ),
			.CPU_mulcam_addr             (CPU_mulcam_addr     ),
			.CPU_mulcam_dout             (CPU_mulcam_dout     ),
			`endif
			//\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
			.multi_addr_en               (multi_addr_en),
			.multi_outport               (multi_outport),
			.multi_outport_en            (multi_outport_en),
			.multi_busy                  (multi_busy),
			//\u521d\u59cb\u5316\u5b8c\u6210
			.multicam_init_done          (multicam_init_done),
			//\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
			.in_buf_val                (in_buf_val),
			.multicast                 (multicast),
			.schedule_start            (schedule_start),
			.frame_info_fifo_empty     (frame_info_fifo_empty),
			.frame_info_fifo_rden      (frame_info_fifo_rden),
			.frame_info_fifo_o         (frame_info_fifo_o),
			.mac_src_addr              (mac_src_addr),
			.mac_des_addr              (mac_des_addr),
			.src_node_ido              (src_node_id_o),
			.ip_src_addr               (ip_src_addr),
			.ip_des_addr               (ip_des_addr),
			//\u4e0e\u961f\u5217\u8c03\u5ea6\u63a5\u53e3
			.mem_que_rdy               (queuesch_init_done),
			.trans_start               (trans_start),
			.discard_start 		   (discard_start),
			.frame_rd_end              (frame_rd_end),
			.trans_ready               (trans_ready),
			.bus_data_o                (bus_data),
			.bus_data_val_o            (bus_data_val),
			.bus_data_end_o            (bus_data_end),
			.frame_len_bus             (frame_len_bus),
			//\u4e0e\u63d2\u5165\u63a5\u53e3
			.rx_rdy_insert             (rx_rdy_insert),
			.rx_ff_sop_insert          (rx_ff_sop_insert),
			.rx_ff_eop_insert          (rx_ff_eop_insert),
			.rx_ff_dval_insert         (rx_ff_dval_insert),
			.rx_ff_dsav_insert         (rx_ff_dsav_insert),
			.rx_ff_data_insert         (rx_ff_data_insert),
			.rx_ff_mod_insert          (rx_ff_mod_insert),
			.insert_empty              (insert_empty),
			.des_node_id_insert        (des_node_id_insert),
			.pri_insert                (pri_insert),
			//\u4e0e\u6355\u83b7\u63a5\u53e3
			.capture_eth_type          (capture_eth_type),
			.capture_rdy               (capture_rdy),
			.capture_data_o            (capture_data_o),
			.capture_dval              (capture_dval),
			.capture_en                (capture_en),
			.cpt_frame_len             (cpt_frame_len)
		);

	receive_schedule inst_receive_schedule (
			.clk                   (clk),
			.rst_n                 (rst_n),
            .ram_2p_cfg_register   (ram_2p_cfg_register),
			//Óë·Ö×é´¦Àí½Ó¿Ú
			.access_fail           (1'b0/*access_fail*/),
			.in_buf_val            (in_buf_val),
			.wr_gnt                (schedule_start),
			.multicast             (multicast),
			.frame_info_fifo_empty (frame_info_fifo_empty),
			.frame_info_fifo_rden  (frame_info_fifo_rden),
			.frame_info_fifo_o     (frame_info_fifo_o),
			.sou_addr              (mac_src_addr),
			.des_addr              (mac_des_addr),
			.sou_id                (src_node_id_o[3:0]),
			.ip_src_addr           (ip_src_addr),
			//.ip_des_addr           (ip_des_addr),
			//Óë×ª·¢±í½Ó¿Ú
			.mac_sour              (mac_sour),
			.port_sour             (port_sour),
			.mac_dest              (mac_dest),
			.uni_busy              (uni_busy),
			.uni_addr_en           (uni_addr_en),
			`ifdef SIM_MODE
			.uni_outport           (4'b0001),  //·ÂÕæ²»ÓÃ²é±í½á¹û£¬Ö»ÓÃ²é±íÊ¹ÄÜ
			`else 
			.uni_outport           (uni_outport),
			`endif
			.uni_outport_en        (uni_outport_en),
			.uni_lookup_fail       (uni_lookup_fail),
            .unicam_init_done      (unicam_init_done),

			.multi_busy            (multi_busy),
			.multi_addr_en         (multi_addr_en),
			.multi_outport         (multi_outport[3:0]),
			.multi_outport_en      (multi_outport_en),
			.multi_ip_src_addr     (/*multi_ip_src_addr*/),
			.multicam_init_done    (multicam_init_done),
			//Óë¶ÓÁÐµ÷¶È½Ó¿Ú
			.rx_fifo_data          (rx_fifo_wdata),
			.rx_fifo_wrreq         (rx_fifo_wren),
			.rx_fifo_full          (rx_fifo_full),
			//ÓëÁ÷¿ØÄ£¿é½Ó¿Ú
			.result			   (result				),
			.result_en		   (result_en			),
			.out_port_num		   (out_port_num		),
			.frame_length_en	   (frame_length_en		),
			.frame_length 		   (frame_length 		),
			.node_flow_num		   (node_flow_num		), 
			.lookup_fail		   (lookup_fail			), 
			.class_flow_ctrl_en	   (class_flow_ctrl_en	),
			.class_flow_ctrl_num   (class_flow_ctrl_num ),
			.do_not_flow_ctrl	   (do_not_flow_ctrl 	)
		);



		flow_ctrl_top_top inst_flow_ctrl_top_top(
			.clk                (clk) ,
			.rst_n              (rst_n) ,
			.clk_cpu            (clk) ,
			.rst_n_cpu          (rst_n) ,
            .ram_dp_cfg_register(ram_dp_cfg_register),
			.node_addr          (node_flow_num) ,
			.node_addr_en       (frame_length_en) ,
			.node_look_fail     (lookup_fail) ,
			.node_out_port_num  (out_port_num) ,
			.frame_length_en    (frame_length_en) ,
			.frame_length       (frame_length) ,
								
			.class_flow_ctrl_en (frame_length_en) ,
			.class_flow_ctrl_num(class_flow_ctrl_num) ,
			.do_not_flow_ctrl   (do_not_flow_ctrl 	),

			.np_data_out        (flc_data_out   ) ,
			.np_data_in         (flc_data_in    ) ,
			.np_addr_in         (flc_addr_in    ) ,
			.np_addr_ctrl       (flc_addr_ctrl  ) ,
			.np_rd_vld          (flc_rd_vld	 	) ,

			.result             (result) ,
			.result_en          (result_en)
		) ;



	schedule_top inst_schedule_top
		(
			.clk                             (clk),
			.rst_n                           (rst_n),
      .ram_2p_cfg_register             (ram_2p_cfg_register),
			//\u521d\u59cb\u5316\u5b8c\u6210
			.init_done                       (queuesch_init_done),
		`ifndef  NO_CPU_MODE
			.np_data_out (sch_data_out   )   ,
    	.np_data_in  (sch_data_in    )   ,
    	.np_addr_in  (sch_addr_in    )   ,
    	.np_addr_ctrl(sch_addr_ctrl  )   ,
			.sch_rd_vld	 (sch_rd_vld	 )	,
		`else 
			.DWRR_en                         (DWRR_en),
			.WEIGHT7                         (WEIGHT7),
			.WEIGHT6                         (WEIGHT6),
			.WEIGHT5                         (WEIGHT5),
			.WEIGHT4                         (WEIGHT4),
			.WEIGHT3                         (WEIGHT3),
			.WEIGHT2                         (WEIGHT2),
			.WEIGHT1                         (WEIGHT1),
			.WEIGHT0                         (WEIGHT0),
			//\u4e0eCPU\u914d\u7f6e\u63a5\u53e3
			.query_CPU_node_minmax_threshold (query_CPU_node_minmax_threshold),
			.CPU_node_minmax_threshold_data  (CPU_node_minmax_threshold_data),
			.query_CPU_queue_max_threshold   (query_CPU_queue_max_threshold),
			.CPU_queue_max_threshold_data    (CPU_queue_max_threshold_data),
			.CPU_BD_public_length            (CPU_BD_public_length),
			.query_CPU_node_min_threshold    (query_CPU_node_min_threshold),
			.CPU_node_min_threshold_data     (CPU_node_min_threshold_data),

			.ro_reg_np_freeblocknumber_register	(						),
			.ro_reg_np_mac_enqueue_cnt 			(						),	   
			.ro_reg_np_mac_enqueue_fail_cnt 	(						), 
			.ro_reg_np_enqueue_num 				(						),
			.ro_reg_np_dequeue_num 				(						),
			.ro_reg_np_max_rx_length			(						),
			.ro_reg_np_max_tx_length			(						),
			.rx_frame_cnt_node_0                (						),
			.rx_frame_cnt_node_1                (						),
			.rx_frame_cnt_node_2                (						),
			.rx_frame_cnt_node_3                (						),
			.rx_frame_cnt_node_4                (						),
			.tx_frame_cnt_node_0                (						),
			.tx_frame_cnt_node_1                (						),
			.tx_frame_cnt_node_2                (						),
			.tx_frame_cnt_node_3                (						),
			.tx_frame_cnt_node_4                (						),	
`endif
			//\u4e0e\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
			.rx_fifo_wdata                   (rx_fifo_wdata),
			.rx_fifo_wren                    (rx_fifo_wren),
			.rx_fifo_full                    (rx_fifo_full),
			//\u4e0e\u5206\u7ec4\u5904\u7406\u63a5\u53e3
			.trans_ready                     (trans_ready),
			.frame_rd_end                    (frame_rd_end),
			.trans_start                     (trans_start),
			.discard_start 			 (discard_start),
			.bus_data_i                      (bus_data[255:0]),
			.bus_data_val_i                  (bus_data_val),
			//.bus_data_end_i                  (bus_data_end),
			//.frame_len_bus                   (frame_len_bus),
			//\u4e0e\u4ea4\u53c9\u8282\u70b9\u7f51\u7edc\u63a5\u53e3
			.uni_tx_rdy0                     (uni_tx_rdy0),
			.uni_tx_rdy1                     (uni_tx_rdy1),
			.uni_tx_rdy2                     (uni_tx_rdy2),
			.uni_tx_rdy3                     (uni_tx_rdy3),
			.mul_tx_rdy0                     (mul_tx_rdy0),
			.mul_tx_rdy1                     (mul_tx_rdy1),
			.mul_tx_rdy2                     (mul_tx_rdy2),
			.mul_tx_rdy3                     (mul_tx_rdy3),
			.emac_data_in                    (emac_data_in),
			.emac_data_wren                  (emac_data_wren),
			.rx_address_dpram                (rx_address_dpram),
			.mac_dest_port_in                (mac_dest_port_in),
			.mul_indicate                    (mul_indicate)
		);
//*********************
//MAIN CORE
//*********************
assign fp_sch_init_done = unicam_init_done & multicam_init_done & queuesch_init_done;

`ifndef NO_CPU_MODE
//\u65b0\u52a0CPU\u8bfb\u53d6\u65f6\u5e8f   2021\u30017\u300130
always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		np_data_out <= 32'b0;
	else if(fp_class_rd_vld)
		np_data_out <= fp_class_data_out;
	else if(sch_rd_vld)
		np_data_out <= sch_data_out;
	else if(flc_rd_vld)
		np_data_out <= flc_data_out;
	else
		np_data_out <= np_data_out;
end
always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		fp_sch_rd_vld <= 1'b0;
	else if(fp_class_rd_vld||sch_rd_vld || flc_rd_vld)
		fp_sch_rd_vld <= 1'b1;
	else
		fp_sch_rd_vld <= 1'b0;
end
`endif

endmodule

